In order to decrease circuit cost, increase circuit density, and increase performance of an integrated circuit, the integrated circuit industry has continually sought to reduce integrated circuit surface area. In markets such as advanced microprocessors and memory circuits, very compact devices are crucial in order to develop future generations of integrated circuits. Fast static random access memory (FSRAM) technology is a portion of the integrated circuit market that has produced a large number of advances in surface area reduction of integrated circuits (ICs). Most of the surface area reductions achieved in FSRAM technology have been due to advances in transistor layout and fabrication.
Initially, transistors in memory cells were fabricated in a conventional, planar manner. In planar technology, memory cell transistors are placed next to each other separated by a physical space limited by photolithographic and other process requirements. Electrical connection between the memory cell transistors is achieved via overlying polysilicon, metal or other conductive layers. The need for larger amounts of memory on an integrated circuit is resulting in a movement away from conventional planar transistors for use in memory designs and designs requiring compact circuits.
The IC industry began to research transistors, especially load transistors, fabricated on a substrate-overlying conductor such as polysilicon. By fabricating transistors overlying the substrate, the substrate could be used for other purposes besides holding load transistors and the surface area of a FSRAM memory cell would therefore decrease.
The substrate-overlying transistors, referred to as thin film transistors (TFTs), mentioned above have been typically manufactured in two ways. The first way is to create a pair of load transistors that are over-gated or top-gated. Over-gated transistors are transistors that each have a source, a drain, and a channel region created from a first polysilicon layer. A gate for this transistor is formed by an overlying second layer of polysilicon. Together, sources, drains, and channel regions in the first polysilicon layer and gates in the second overlying polysilicon layer form pairs of load transistors for an FSRAM cell resulting in reduced cell surface area.
The second way in which thin film transistors have been made is by under-gated or bottom-gated polysilicon transistors. Under-gated transistors are transistors that have a source, a drain, and a channel region created from a second polysilicon layer. A gate for this type of transistor is formed by an underlying first layer of polysilicon. Together, sources, drains, and channel regions in the first polysilicon layer and gates in the second underlying polysilicon layer form pairs of load transistors for an FSRAM cell resulting in reduced cell surface area.
Although over-gated pairs of transistors and under-gated pairs of transistors helped to reduce memory cell surface area, these pairs of transistors may not be capable of providing circuit densities necessary for future generations of FSRAM cells. In addition, most of the conventional TFT pair designs contain three to five contacts, and the etch steps required to etch some of these contact openings are not trivial. A pair of load transistors with reduced surface area or improved operational performance is needed for future memory generations.